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LFSR

Linear Feedback Shift Register is a fundamental pseudo-random sequence generator widely used in hardware testing, stream ciphers, and error correction. Uses shift-and-XOR operations with a primitive polynomial to generate maximal-length sequences with period 2^n-1.

Properties

Property	Value
Category	Random Number Generators
Sub-category	Deterministic PRNG
Security status	🎓 Educational Only
Complexity	Beginner
Inventor	Solomon W. Golomb (formalized)
Year	1967
Origin	🇺🇸 United States
Source	algorithms/random/lfsr.js

Parameters

Parameter	Supported values
Seed sizes	1 byte (8 bits) to 8 bytes (64 bits)

Capabilities

Flag	Value
IsDeterministic	Yes
IsCryptographicallySecure	No

Security

Status: 🎓 Educational Only

No vulnerabilities are recorded for this implementation.

Documentation

• Golomb: Shift Register Sequences (1967)
• Philip Koopman: Maximal Length LFSR Feedback Terms
• Stahnke: Primitive Binary Polynomials (1973)
• Analog Devices: PRNG Using LFSR
• Wikipedia: Linear-feedback shift register

References

• Watson: Primitive Polynomials (Mod 2) - 1962
• Živković: A Table of Primitive Binary Polynomials (1994)

Test vectors

7 vectors ship with this algorithm and run in the test suite. Byte values are hexadecimal.

Vector 1 — Seed 0x0000000000000042: First 8 bytes - minimal seed with tapped bits set

Field	Value
seed	0000000000000042
outputSize	8
input	null
expected	2100000000000000

Vector 2 — Seed 0x0123456789ABCDEF: First 8 bytes - standard test pattern

Field	Value
seed	0123456789abcdef
outputSize	8
input	null
expected	f7e6d5c4b3a29180

Vector 3 — Seed 0xFFFFFFFFFFFFFFFF: First 8 bytes - all ones seed

Field	Value
seed	ffffffffffffffff
outputSize	8
input	null
expected	ffffffffffffffff

Vector 4 — Seed 0x0123456789ABCDEF: First 16 bytes - sequence continuation test

Field	Value
seed	0123456789abcdef
outputSize	16
input	null
expected	f7e6d5c4b3a2918080691bb1a25b9478

Vector 5 — Seed 0x8000000000000000: First 8 bytes - high bit set

Field	Value
seed	8000000000000000
outputSize	8
input	null
expected	0000000000000040

Vector 6 — Seed 0xAAAAAAAAAAAAAAAA: First 8 bytes - alternating bit pattern

Field	Value
seed	aaaaaaaaaaaaaaaa
outputSize	8
input	null
expected	55555555555555d5

Vector 7 — Seed 0x1111111111111111: First 8 bytes - sparse bit pattern

Field	Value
seed	1111111111111111
outputSize	8
input	null
expected	8888888888888808

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